Rubin2020_PCW slack archives day2-tue-slot2a-rrb-camera 2020-07-31---2020-08-11

Fri 2020-07-31 08:10PM

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Melissa Graham Fri 2020-07-31 08:10PM

@Melissa Graham set the channel purpose: Rubin Research Bytes Session A. Camera

Melissa Graham Fri 2020-07-31 08:35PM

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Melissa Graham Fri 2020-07-31 08:36PM

@Melissa Graham has renamed the channel from "day2-tue-slot-2a-rrb-camera" to "day2-tue-slot2a-rrb-camera"

Melissa Graham Sat 2020-08-01 01:14PM

@Melissa Graham set the channel topic: Rubin Research Bytes Session A. Camera
RRB Webpage:
<https://project.lsst.org/meetings/rubin2020/agenda/session/rubin-research-bytes>

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Simon Krughoff Tue 2020-08-11 01:37PM

@Andrew Bradshaw is it possible to project spot patterns with the pinhole setup?

Andrew Bradshaw Tue 2020-08-11 01:39PM: Yes absolutely, either from reflected light off hi-res printed scenes, or light transmission through film or paper. We could have whatever scenes we like!
Simon Krughoff Tue 2020-08-11 01:40PM: Cool!

Tue 2020-08-11 01:37PM

@Andrew Bradshaw has joined the channel

Melissa Graham Tue 2020-08-11 01:49PM

@here new transition time 11:15am due to technical difficulties

Robert Lupton Tue 2020-08-11 01:54PM

Question for Adam: how well does your CTE model separate traps on the serial from every-transfer classical CTE? I think your model separates the two components

Michael Reuter Tue 2020-08-11 02:08PM

Thanks to all the speakers. :clap:

Chuck Claver Tue 2020-08-11 02:21PM

Q; Is the pinhole fixed in X-Y or can it be translated relative to the FPA?

Andrew Bradshaw Tue 2020-08-11 02:32PM: The pinhole projector could be placed on the same XY stage that the narrow beam uses, ~300mm from L1, though it is currently shown as being at the bottom of the dark box.

Wesley Fraser Tue 2020-08-11 02:24PM

Question for Adam - relatively, how large are the anticipated astrometric effects from the sensor compared to the effects of telescope OTA distortion?

Robert Lupton Tue 2020-08-11 02:25PM

Answer from Robert: As for DECam, we'll separate the effects. So they shouldn't show up in your data

mrawls Tue 2020-08-11 02:29PM

2-part Q for any/all presenters: What has been most surprising for you between how you expected LSSTCam to behave vs. how it is actually behaving so far? What are you most looking forward to investigating once ComCam is on the telescope?

Chuck Claver Tue 2020-08-11 02:30PM

:clap:

Colin Slater Tue 2020-08-11 02:31PM

Q for Andrew: how flat is a pinhole flat? And what's the dominant source of non-flatness?

Andrew Bradshaw Tue 2020-08-11 02:40PM

The pinhole images taken during 9 raft testing indicate very flat projection is possible. Attached image shows several sensors across the final plane. In theory most of the non flatness of pinhole images comes from the thickness of the pinhole substrate

Colin Slater Tue 2020-08-11 02:44PM

Ahh very cool

Colin Slater Tue 2020-08-11 02:43PM

just to follow on the astrometric discussion, optical distortions are coherent over much larger angular scales than the pixel distortions. So I suspect relative absolute magnitudes isn't really the key metric for which one is "worse"; they have different methods and levels of "correctability"

Chuck Claver Tue 2020-08-11 02:45PM: Yes - the astrometry distortions from the atmosphere are a bigger concern - since they are on a smaller angular scale and vary with time.

Margaux Lopez Tue 2020-08-11 02:49PM

@here Thank you to all the speakers and all who attended, feel free to keep the conversation going here. Happy Tuesday!

Colin Slater Tue 2020-08-11 02:49PM

Double checking that I understood HyeYun's (not on slack?) last statement correctly, ITL and E2V get their boules from the same vendor? Out of curiosity, who makes the boules?

Dan Weatherill Tue 2020-08-11 02:49PM

thanks @Margaux Lopez and @Steve Ritz for hosting the session

Dan Weatherill Tue 2020-08-11 02:51PM

@Colin Slater I used to work closely with e2v and don't know if they've changed their supplier since then so wouldn't say a name for fear of being incorrect. However, the silicon is both extremely high resistivity, and bulk construction (i.e. there is no epi layer in these devices) which makes it both very expensive and not used much in many processes. It wouldn't surprise me at all that there are few if not only one supplier of such wafers

Colin Slater Tue 2020-08-11 02:54PM: Interesting! Thanks, I'm always curious to hear some of the behind-the-scenes details like that
Dan Weatherill Tue 2020-08-11 02:55PM: it will almost certainly be float zone rather than Czoralski silicon, and that's not so much a problem for e2v Chelmsford, where their fab is state of the art for the mid 80s and only capable of processing 6" wafers. I don't doubt that ITL has a similar arrangement
Colin Slater Tue 2020-08-11 03:06PM: Heh, guess it pays to keep some older tech around for niche cases like this
Dan Weatherill Tue 2020-08-11 03:06PM: overlapping gate CCDs will never be able to make you enough money to afford a modern fab!
Colin Slater Tue 2020-08-11 03:08PM: Ah! that was the other question I had: I don't understand when you talked about "changing" the gate size; isn't that physically built into the device?
Dan Weatherill Tue 2020-08-11 03:08PM: yes,
Dan Weatherill Tue 2020-08-11 03:08PM: but since there are a series of 3 (in ITL case) or 4 (in e2v case) gates per pixel, you can choose different combinations of how many to have energised during integration
Dan Weatherill Tue 2020-08-11 03:08PM: this in effect changes the gate width
Dan Weatherill Tue 2020-08-11 03:12PM: any combination is allowed, so long as at least one gate is not energised during integration (as this would turn your CCD into an incredibly expensive photodiode with an overcomplicated readout process)
Colin Slater Tue 2020-08-11 03:13PM: Oh, and they're different sizes, so that gives you more combinations to mix-and-match
Dan Weatherill Tue 2020-08-11 03:14PM: the manufacturing feature size in the e2v process is 1um, the pixels are 10um, there are 4 gates. The exact sizes are proprietary information I believe but that doesn't give you many choices
Colin Slater Tue 2020-08-11 03:14PM: is there a cost in full-well capacity for having more gates energized?
Dan Weatherill Tue 2020-08-11 03:14PM: yes and no,
Dan Weatherill Tue 2020-08-11 03:14PM: changing number of gates energised certainly changes the position of blooming full well in the pixel
Dan Weatherill Tue 2020-08-11 03:15PM: but if one were so inclined it can be re-adjusted by changing the image clock voltages
Dan Weatherill Tue 2020-08-11 03:15PM: that being said, provided you have the image clocks high enough, with most devices in general more gates would be higher full well capacity
Dan Weatherill Tue 2020-08-11 03:16PM: ( in our tests we didn't re-optimise image clock at each gate width, for fairness, since image clock voltage might also very slightly affect brighter-fatter effect coefficients)
Dan Weatherill Tue 2020-08-11 03:17PM: there do exist devices where having all the possible parallel gates "high" during integration would result in a well capacity bigger than the serial register can handle, making this configuration useless. This isn't the case in LSST camera devices, at least e2v ones
Dan Weatherill Tue 2020-08-11 03:18PM: you do not want the serial register to bloom sideways before the pixels bloom up the column
Colin Slater Tue 2020-08-11 03:19PM: ohh right, the gates are setting the potential barrier, of course. I was thinking in terms of the remaining area of the pixel being available for collecting charge. Ok, that makes a lot of sense
Colin Slater Tue 2020-08-11 03:19PM: and yeah, serial blooming does super weird things

Steve Ritz Tue 2020-08-11 02:54PM

Thanks to all the speakers and participants.

Robert Lupton Tue 2020-08-11 02:58PM

I'd heard that both manufacturers had enough good Si from one vendor to make all the first-gen CCDs. If we had enough process failures there was worry that they'd have to go back for another batch which might not have been so good.